1. Field of the Invention
The present invention generally relates to semiconductor integrated circuit devices and semiconductor memory devices and, more particularly, to a semiconductor integrated circuit device and a semiconductor memory device comprising two internal circuits respectively energized by two power supply voltages which can be applied in different timing. The present invention has a particular applicability to Dynamic Random Access Memories (DRAMs) having multi-bits configurations.
2. Description of the Background Art
Recently, high integration of a semiconductor memory has been realized, and storage capacity of the semiconductor memory has been increased. The demand for the semiconductor memory having multi-bits configuration is increased as the storage capacity increases. The semiconductor memory having multi-bits configuration can handle data, for example in 1 byte (8 bits) or in 2 bytes (16 bits) unit. It means that the semiconductor memory having multi-bits configuration can simultaneously read and write a plurality of bits of data.
Generally, a number of semiconductor memories are placed on a printed circuit board (memory board), and their data output terminals are connected to data buses. Accordingly, when data stored in a semiconductor memory is read out, the semiconductor memory drives a data bus (load) connected to a data output terminal in response to the read out data signal. In order to drive the data bus, the semiconductor memory comprises at its output stage a driving circuit for driving the data bus. Generally, the load which must be driven by the driving circuit is large, since the long data bus is provided on the memory board. Therefore, the driving circuit is constructed by a transistor having large current driving capability.
Since the driving circuit provided in the semiconductor memory needs to drive such a large load as mentioned above, it consumes much current, i.e., power. When a signal power supply voltage is supplied not only to the primary circuits constituting the semiconductor memory, namely, a memory cell array and a sense amplifier, but to the driving circuit, a power supply voltage level is decreased by current consumption in the driving circuit. The decrease of the power supply voltage causes malfunction of the main circuits in the semiconductor memory. Recently, for the purpose of preventing the decrease of the power supply voltage supplied to the primary circuits, additional power supply voltage for the driving circuit is applied to the semiconductor memory. Therefore, although the driving circuit consumes much current, malfunction of the main circuits in the semiconductor memory caused by that current consumption can be avoided.
Furthermore, the semiconductor memory supplied with two power supply voltages also has an advantage in view of noise control as mentioned in the following description. When a single power supply voltage is supplied, it is difficult to transmit noise in the semiconductor memory to the power supply, that is, noise hardly escapes, since impedance of a gold line connected between a power supply lead and a bonding pad formed in the semiconductor substrate is high. Therefore, in this case, peripheral circuits in the semiconductor memory are easily affected by noise. However, when two or more power supply voltages are supplied, noise is easily transmitted to the power supply, that is, from the semiconductor memory to outside (noise easily escapes), since the total impedance of two or more gold lines is decreased. As a result, peripheral circuits in the semiconductor memory are rarely affected by noise.
In view of the advantages mentioned above, two or more power supply voltages are applied to recent semiconductor memories having multi-bits configurations. A plurality of power supply voltages are supplied to the semiconductor memory through a plurality of power supply lines provided on the memory board, but their timings are often different from each other, because the plurality of power supply lines have different lengths and hence different impedances. As a result, even if a plurality of power supply voltages are simultaneously provided to the memory board, the timings of these power supply voltages supplied to the semiconductor memory often differ. It should be noted that, depending on the situation, there may be a case where one of a plurality of power supply voltages is not supplied because of some failure.
In the following description, at first, the semiconductor memory will be described. Next, there will be a description of possible problems caused when the timings of a plurality of power supply voltages differ, or when one of the power supply voltages is not applied. The present invention is generally applicable to the semiconductor memories, and a dynamic random access memory (referred to as "DRAM" hereinafter) will be described as one example in the following description.
FIG. 7 is a block diagram of a conventional DRAM. Referring to FIG. 7, the DRAM 1a comprises a main circuit 2a energized by an externally applied first power supply voltage Vcc 1, and an output driving circuit 4 energized by a second power supply voltage Vcc 2. Main circuit 2a comprises a memory cell array 60 including memory cells arranged in rows and columns, an address input buffer 63 for receiving externally applied address signals A0 to Am, a row decoder 61 for decoding a row address signal RA, a column decoder 62 for decoding a column address signal CA, and a sense amplifier 64 for amplifying data signals read out from memory cells. Sense amplifier 64 is connected to an output buffer circuit 3a and to an input latch circuit 65 through an IO line.
A clock signal generator 67 generates various control signals for controlling DRAM 1a in response to an externally applied row address strobe signal /RAS and a column address strobe signal /CAS. An OE buffer 68 receives an externally applied output enable signal /OE to provide a signal OEM. A power on reset circuit 69 is supplied with power supply voltage Vcc 1 to generate a power on reset signal (referred to as "POR" hereinafter).
Output driving circuit 4 is supplied with second power supply voltage Vcc 2 to drive a load connected to I/O terminals DQ1 to DQn, namely, a data bus DB in response to n-bit data signals generated from output buffer circuits 3a. I/O latch circuit 65 is connected to I/O terminals DQ1 to DQn through a bypass line bypassing output driving circuit 4.
In write operation, since a write enable signal /W falls, n-bit data signals applied through terminals DQ1 to DQn are latched in latch circuit 65. The latched signals are written into the memory cell designated by external address signals A0 to Am. In read operation, n-bit stored data signals are read out from the memory cell designated by external address signals A0 to Am. Output buffer circuit 3a applies n-bit data signals to output driving circuit 4 in response to output enable signal /OE. Output driving circuit 4 drives data bus DB connected to terminals DQ1 to DQn in response to the applied data signals.
FIG. 8 is a circuit diagram of an output main amplifier 3ai provided in an output buffer circuit 3a and a circuit 4i provided in output driving circuit 4 shown in FIG. 7. Circuits 3ai and 4i handle 1 bit read out data signal, namely, an ith data signal RDi. In other words, output buffer circuit 3a and output driving circuit 4 shown in FIG. 7 comprise n-circuits 3ai and 4i shown in FIG. 8.
Referring to FIG. 8, a first stage circuit 5 comprises PMOS transistors 11 and 12, and NMOS transistors 13 and 14 connected in series between power supply voltage Vcc 1 and ground Vss 1. The ith read out data signal RDi is applied to the gates of transistors 12 and 13 constituting an inverter. First stage circuit 5 is activated in response to data obtaining signals DOT and /DOT generated from clock signal generator 67 shown in FIG. 7, to apply read out data signal RDi to a latch circuit 6. Latch circuit 6 comprises two cross coupled CMOS inverters. One CMOS inverter is constituted by a PMOS transistor 15 and a NMOS transistor 16. The other CMOS inverter is constructed by a PMOS transistor 17 and an NMOS transistor 18. Latch circuit 6 applies mutually inverted two signals to a CMOS inverter constructed by a PMOS transistor 19 and an NMOS transistor 20, and to a CMOS inverter constructed by a PMOS transistor 21 and an NMOS transistor 22. These two signals provided from the two CMOS inverters are applied to output timing control circuits 7 and 8, respectively.
Output timing control circuit 7 is constructed by PMOS transistors 23 and 24, and NMOS transistors 25 and 26. When externally applied output enable signal /OE is at a low level, and OE buffer 68 shown in FIG. 7 provides a high level signal OEM. Transistors 24 and 25 are turned off and on, respectively, in response to signal OEM. Accordingly, at this time, output timing control circuit 7 transmits the signal applied to an input node N1 to CMOS inverter 9. When output enable signal /OE is at a high level, transistors 24 and 25 are turned on and off, respectively. Accordingly, at this time, circuit 7 applies a high level signal to inverter 9. Inverter 9 applies a low level signal S1 to driver circuit 4i in response to the applied high level signal.
Output timing control circuit 8 has the same circuit configuration and operates in the same manner as circuit 7. Accordingly, when a high level signal OEM is applied, circuit 8 applies to CMOS inverter 10 an inverted one of the signal applied to a node N2. Therefore, at this time, inverter 10 provides inverted signal S2 and applies it to driving circuit 4i . Since transistors 28 and 29 are turned on and off, respectively when signal OEM is at a low level, CMOS inverter 10 provides a low level signal S2.
Driving circuit 4i comprises NMOS transistors Q1 and Q2 connected in series between second power supply voltage Vcc 2 and ground Vss 2. A common connection node ccn of transistors Q1 and Q2 is connected to ith data I/O terminal DQi. When output enable signal /OE is at a low level, mutually inverted data signals S1 and S2 are applied to transistors Q1 and Q2, respectively, in response to a high level signal OEM. Consequently, either one of transistors Q1 and Q2 is turned on, and either one of the potential Vcc 2 and Vss 2 in response to ith read out data RDi is provided through terminal DQi.
When second power supply voltage Vcc 2 is applied without any supply of first power supply voltage Vcc 1, there will be a problem as mentioned in the following description. When first power supply voltage Vcc 1 is not applied, output signals S1 and S2 of inverters 9 and 10 indicate an unstable potential. Accordingly, conductive/non conductive state of transistors Q1 and Q2 in driving circuit 4i become unstable. As a result, current consumption is increased, because a penetrating current flows from power supply voltage Vcc 2 to ground Vss 2 through transistors Q1 and Q2. Depending on the situation, transistors Q1 and Q2 may be damaged because of excessive penetrating current.
FIG. 9 shows a timing chart indicating the flow of an excessive penetrating current when the supply of power supply voltages Vcc 1 and Vcc 2 starts. Referring to FIG. 9, the supply of power supply voltage Vcc 2 starts at the time t1, and then the supply of power supply voltage Vcc 1 starts at the time t2. Therefore, output signals S1 and S2 provided from output main amplifier circuit 3ai show unstable potential until the time t2. Since power supply voltage Vcc 1 is applied to output main amplifier 3ai after the time t2, the potential of the output signals S1 and S2 is established. Therefore, it should be noted that an excessive penetrating current Ip can flow through the transistors Q1 and Q2 in driving circuit 4i until the time when power supply voltage Vcc 1 rises (t2) after the end of the rise of power supply voltage Vcc 2 (t1).
FIG. 10 shows a timing chart indicating the flow of the excessive penetrating current when the supply of power supply voltages Vcc 1 and Vcc 2 ends. Referring to FIG. 10, the supply of power supply voltage Vcc 1 ends at the time t11, and then the supply of power supply voltage Vcc 2 ends at the time t14. Therefore, output signals S1 and S2 of output main amplifier circuit 3ai show unstable potential. As a result, excessive penetrating current Ip can flow through transistors Q1 and Q2 in driving circuit 4i in the period between the time t11 and t14.